Designing and verifying 32-bit RISC-V processor implementing RV32I
Led by Harshbir Singh
The objective of this project was to design a complete 32-bit RISC-V (RV32I) single-cycle processor from scratch at the register-transfer level using SystemVerilog. The architecture follows a Harvard model with separate instruction and data memories and executes all 37 unprivileged instructions – defined in RV32I - in a single clock cycle. Core components include a 32-bit ALU supporting arithmetic, logical, and shift operations, a multi-source immediate generator, a register file, and a combinational control unit that drives an 11-signal control interface. The datapath integrates multiple multiplexers to manage instruction flow across fetch, decode, execute, memory, and writeback stages, with timing constrained by load operations. The design was rigorously verified through modular testbenches and full-system simulation using Xilinx Vivado.
