Our Projects

Designing and simulating a 8-bit ALU

The core objective of this project was to design and functionally verify an 8-bit Arithmetic Logic Unit (ALU) using behavioral Verilog HDL. As a fundamental component of a Central Processing Unit (CPU), the ALU is responsible for executing both arithmetic and logical operations.

CNN customized for FPGA deployment

Led by Rakshit Arora

This project focuses on designing a highly efficient Convolutional Neural Network (CNN) for image classification on the CIFAR-10 dataset. Through an iterative design process, the architecture was optimized to balance high accuracy with low computational complexity, making it suitable for hardware deployment on Field Programmable Gate Arrays (FPGAs).